I have a single clock to monitor, I need to detect stable frequencies and glitches using Assertion

SystemVerilog
1

There is condition with N number of pulses having same width, then we can consider the frequency is stable. If I detect unstable frequency while clock switching, I need to save the pulse width of stable frequency and start monitoring for next stable frequency. If I detect any shorter pulse width in between stable frequencies by comparing their pulse widths, I need to assert failure. I thought of using functions and recursive properties. I am not able to figure out.

2

In reply to Vishwasu Deshpande:

you can assert property like below to check positive pulse >= 100;



logic a;

property checking_pulse_duration;
   realtime val;
    @ (a) (a, val = $realtime) |=> ($realtime - val >= 100);
endproperty

assert property (checking_pulse_duration)
else $error("Error!");
3

In reply to javatea:

Thanks for the response. However I have no knowledge of expected pulse width. I only can monitor a clock, look when it first provides N stable pulse widths, consider that first stable frequency, look for switching with irregular pulse widths and then look for N stable pulse width again. Next compare first middle and last frequencies to see if it glitched.

4

In reply to Vishwasu Deshpande:

Do you have a faster reference clock to count the width, or are you just trying to measure realtime?

When you find an irregular pulse, does that become the first of N pulses to check?

Does this need to be coded as an assertion (very difficult) or can any kind of checking code be used?

5

In reply to dave_59:

I do not have a reference clock. I have to measure real time. The environment is legacy, so either I have option sv module or verilog module or assertions. I have coded a Recursive assertion but not tested yet.

property p1 (start, stop, local prev_diff, int_diff, last_diff, int_freq, p_id);

start: Can be posedge clk or negedge clk
stop: Can be negedge clk or posedge clk respectively.
prev_dif: previous difference before the clock has irregular pulse, meaning before it starts to switch.
int_diff: lowest pulse width while clock is switching.
last diff: previous diff to keep comparing.
int_freq: indicator that clock is switching.
p_id: property id so that another property is not triggered while one property is checking. A global check in progress variable and ID are set. Only the recursive call gets the ID.

I monitor the clock for pulse widths, need to look for both high/low. When I find irregular pulses, I set a variable int_freq and look for lowest pulse width. Once within switching period, I find stable pulses, I compare if the lowest width while switching is lower than prev or current diff.