I have a single clock to monitor, I need to detect stable frequencies and glitches using Assertion

SystemVerilog
2

In reply to Vishwasu Deshpande:

you can assert property like below to check positive pulse >= 100;



logic a;

property checking_pulse_duration;
   realtime val;
    @ (a) (a, val = $realtime) |=> ($realtime - val >= 100);
endproperty

assert property (checking_pulse_duration)
else $error("Error!");