I am getting infite loop when run this code. And cannot understand why I am getting infinite loop

SystemVerilog
, ,
1 
module xyz;
  bit [9:0] sel;
  bit [1:0] dev;
  
  initial begin
    for(sel=0;sel<=9;sel++)
      begin
        if(sel==0 || sel==5) $display("sel==%b",sel);
        else
          for(dev=0;dev<=3;dev++)
            begin
              $display("dev=%b , sel==%b",dev,sel);
            end
      end    
  end
endmodule
2

In reply to prafulborad3@gmail.com:

dev is 2-bits and cannot be greater than 3.

3

okay…
i know dev value are between 0 to 3
and i dont want the value of dev is greater than 3
but i don’t understand the reason of infinite loop.

4

In reply to prafulborad3@gmail.com:

Can you explain how you think it should get out of the loop?

5

In reply to avpchandra:

Don’t need to. As Dave said, the problem because dev was declared 2 bits. To exit the for loop “for(dev=0;dev<=3;dev++)”, the value of dev must > 3, this will never happen when you declared dev 2 bits, value of dev: 0 - 1 - 2 - 3 - 0, and so on.