I am doing uvm adder varification but i have got some error

UVM
1

class seq_item extends uvm_sequence_item;
`uvm_object_utils(seq_item)
rand bit [1:0]a;
rand bit [1:0]b;
rand bit c;
bit [2:0]sum;

 function new(string name="seq_item");
	 super.new(name);
 endfunction

endclass

import uvm_pkg::uvm_sequence;

class base_seq extends uvm_sequence#(seq_item);
seq_item tx;
`uvm_object_utils(base_seq)

function new(string name=“base_seq”);
super.new(name);
endfunction
task body();

  repeat(2) begin
    
   tx=seq_item::type_id::create("tx",this);
   
   start_item(tx);
    assert(tx.randomize);
    tx.print();
   finish_item(tx);
  end

 endtask

endclass

class sequencer extends uvm_sequencer#(seq_item);

 `uvm_component_utils(sequencer)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction

endclass

class driver extends uvm_driver#(seq_item);
seq_item tx;

virtual intf vif;

 `uvm_component_utils(driver)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction

function void build_phase(uvm_phase phase);
void’(uvm_config_db #(virtual intf)::get(this,“”,“pif”,vif));
endfunction

 task run_phase(uvm_phase phase);
     forever begin
         seq_item_port.get_next_item(tx);
            vif.a=tx.a;
            vif.b=tx.b;
            vif.c=tx.c;
            @(negedge vif.clk); 
         seq_item_port.item_done();

     end
 endtask

endclass

class monitor extends uvm_monitor;
virtual intf vif;
seq_item tx;
uvm_analysis_port#(seq_item) port;

`uvm_component_utils(monitor)

function new(string name,uvm_component parent);

     super.new(name,parent);

endfunction

function void build_phase(uvm_phase phase);
void’(uvm_config_db#(virtual intf)::get(this,“”,“pif”,vif));
port=new(“port”,this);
tx=seq_item::type_id::create(“tx”,this);

endfunction

task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk);
tx.a=vif.a;
tx.b=vif.b;
tx.c=vif.c;
tx.sum=vif.sum;
port.write(tx);

 end

endtask

endclass

class agent extends uvm_agent;
sequencer sqr;
driver dvr;
monitor mon;
`uvm_component_utils(agent)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction
 function void build_phase(uvm_phase phase);
     sqr=sequencer::type_id::create("sqr",this);
     dvr=driver::type_id::create("dvr",this);
     mon=monitor::type_id::create("mon",this);
 endfunction
 function void connect_phase(uvm_phase phase);
 
     dvr.seq_item_port.connect(sqr.seq_item_export);
 endfunction

endclass

class scoreboard extends uvm_scoreboard;
seq_item tx;
uvm_analysis_imp#(seq_item,scoreboard) imp;
bit [4:0]sum;

`uvm_component_utils(scoreboard)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
imp=new(“imp”,this);
tx=seq_item::type_id::create(“tx”,this);

endfunction

function void write(seq_item tx1);
this.tx=tx1;

   sum=tx.a + tx.b +tx.c; 

    
    if(sum == tx.sum)
  		$display( "Result match","tx.sum=%0d & sum=%0d ",tx.sum,sum);
	    else
  		$display( "Result misMatch","tx.sum=%0d &  sum=%0d ",tx.sum,sum);

endfunction
endclass

class env extends uvm_env;
agent agent1;
scoreboard sb;

 `uvm_component_utils(env)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction



 function void build_phase(uvm_phase phase);
     agent1=agent::type_id::create("agent1",this);
     sb=scoreboard::type_id::create("sb",this);
     
 endfunction

 function void connect_phase(uvm_phase phase);
         agent1.mon.port.connect(sb.imp);
         
 endfunction

endclass

class base_test extends uvm_test;
env env1;
base_seq seq;

 `uvm_component_utils(base_test)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction
 function void build_phase(uvm_phase phase);
     env1=env::type_id::create("env1",this);
           seq=base_seq::type_id::create("seq",this);
         
 endfunction



 task run_phase(uvm_phase phase);
   phase.raise_objection(this);

    seq.start(env1.agent1.sqr);
     
   phase.drop_objection(this);

 endtask

endclass

include "uvm_pkg.sv" include “uvm_macros.svh”
import uvm_pkg::*;

include "interface.sv" include “dut.sv”
include "seqitem.sv" include “sequence.sv”
include "driver.sv" include “monitor.sv”
include "sequencer.sv" include “agent.sv”

include "scoreboard.sv" include “env.sv”

module top;

`include “test.sv”
bit clk;
intf pif(clk);

adder dut(pif);

initial begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),“*”,“pif”,pif);
run_test(“base_test”);
end

initial begin
clk=0;
forever #5 clk=~clk;
end

endmodule

I have got 2 errors and 9 warning

** Error: (vsim-7065) Illegal assignment to class work.uvm_pkg::uvm_component from class work.top_sv_unit::base_seq

Time: 0 ns Iteration: 0 Region: /top_sv_unit::base_seq File: sequence.sv Line: 14

** Error: (vsim-8754) Actual input arg. of type ‘class work.top_sv_unit::base_seq’ for formal ‘parent’ of ‘create’ is not compatible with the formal’s type ‘class work.uvm_pkg::uvm_component’.

Time: 0 ns Iteration: 0 Region: /top_sv_unit::base_seq File: sequence.sv Line: 14

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_dpi_get_next_arg_c’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_dpi_get_tool_name_c’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_dpi_get_tool_version_c’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_dpi_regcomp’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_dpi_regexec’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_dpi_regfree’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_dump_re_cache’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

** Warning: (vsim-3770) Failed to find user specified function ‘uvm_glob_to_re’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/uvm_pkg.sv

Error loading design

Error loading design

End time: 09:32:17 on Jul 14,2021, Elapsed time: 0:00:23

Errors: 2, Warnings: 9

please tell where is it comming and why

2

In reply to taufeeq_khan:

Seems like some simulator related issue?

i have modified your code a bit, this might help you.

tx=seq_item::type_id::create(“tx”,this); → sequence_item takes only name as argument

import uvm_pkg::*;
`include "uvm_macros.svh"


class seq_item extends uvm_sequence_item;
`uvm_object_utils(seq_item)
rand bit [1:0]a;
rand bit [1:0]b;
rand bit c;
bit [2:0]sum;

function new(string name="seq_item");
super.new(name);
endfunction

endclass


class base_seq extends uvm_sequence#(seq_item);
seq_item tx;
`uvm_object_utils(base_seq)

function new(string name="base_seq");
super.new(name);
endfunction
task body();

repeat(2) begin

tx=seq_item::type_id::create("tx");

start_item(tx);
assert(tx.randomize);
tx.print();
finish_item(tx);
end

endtask

endclass

class sequencer extends uvm_sequencer#(seq_item);

`uvm_component_utils(sequencer)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

endclass

class driver extends uvm_driver#(seq_item);
seq_item tx;

virtual intf vif;

`uvm_component_utils(driver)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
void'(uvm_config_db #(virtual intf)::get(this,"","pif",vif));
endfunction

task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk);
seq_item_port.get_next_item(tx);
vif.a=tx.a;
vif.b=tx.b;
vif.c=tx.c;
seq_item_port.item_done();

end
endtask

endclass


class monitor extends uvm_monitor;
virtual intf vif;
seq_item tx;
uvm_analysis_port#(seq_item) port;

`uvm_component_utils(monitor)

function new(string name,uvm_component parent);

super.new(name,parent);

endfunction

function void build_phase(uvm_phase phase);
void'(uvm_config_db#(virtual intf)::get(this,"","pif",vif));
port=new("port",this);
tx=seq_item::type_id::create("tx",this);

endfunction

task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk);
tx.a=vif.a;
tx.b=vif.b;
tx.c=vif.c;
tx.sum=vif.sum;
port.write(tx);



end
endtask

endclass

class agent extends uvm_agent;
sequencer sqr;
driver dvr;
monitor mon;
`uvm_component_utils(agent)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
sqr=sequencer::type_id::create("sqr",this);
dvr=driver::type_id::create("dvr",this);
mon=monitor::type_id::create("mon",this);
endfunction
function void connect_phase(uvm_phase phase);

dvr.seq_item_port.connect(sqr.seq_item_export);
endfunction

endclass

class scoreboard extends uvm_scoreboard;
seq_item tx;
uvm_analysis_imp#(seq_item,scoreboard) imp;
bit [4:0]sum;

`uvm_component_utils(scoreboard)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
imp=new("imp",this);
tx=seq_item::type_id::create("tx",this);

endfunction

function void write(seq_item tx1);
this.tx=tx1;

sum=tx.a + tx.b +tx.c;


if(sum == tx.sum)
$display( "Result match","tx.sum=%0d & sum=%0d ",tx.sum,sum);
else
$display( "Result misMatch","tx.sum=%0d & sum=%0d ",tx.sum,sum);

endfunction
endclass

class env extends uvm_env;
agent agent1;
scoreboard sb;


`uvm_component_utils(env)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
agent1=agent::type_id::create("agent1",this);
sb=scoreboard::type_id::create("sb",this);

endfunction

function void connect_phase(uvm_phase phase);
agent1.mon.port.connect(sb.imp);

endfunction

endclass

class base_test extends uvm_test;
env env1;
base_seq seq;

`uvm_component_utils(base_test)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
env1=env::type_id::create("env1",this);
seq=base_seq::type_id::create("seq",this);

endfunction

task run_phase(uvm_phase phase);
phase.raise_objection(this);

seq.start(env1.agent1.sqr);

phase.drop_objection(this);

endtask

endclass


interface intf(input bit clk);
logic [1:0]a,b;
logic c;
logic [2:0]sum;
endinterface


module adder(intf vif);
//always @(posedge vif.clk)
//begin
assign vif.sum=vif.a+vif.b+vif.c;
//end
endmodule

module top;

bit clk;
intf pif(clk);

adder dut(pif);

initial begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),"*","pif",pif);
run_test("base_test");
end

initial begin
clk=0;
forever #5 clk=~clk;
end

endmodule
3

In reply to vardhana:

This line will be the cause of your error:

seq=base_seq::type_id::create("seq",this);

Please correct to

seq=base_seq::type_id::create("seq");
4

In reply to chr_sue:

In reply to vardhana:
This line will be the cause of your error:

seq=base_seq::type_id::create("seq",this);

Please correct to

seq=base_seq::type_id::create("seq");

Yea, right. i didnot check that.
but was wondering, why the simulator didnot throw any error?

5

In reply to chr_sue:

thanks for reply
now this error is comming
Fatal: (vsim-160) /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh(27): Null foreign function pointer encountered when calling ‘uvm_dpi_get_next_arg_c’

Time: 0 ns Iteration: 0 Process: /uvm_pkg/#INITIAL#619 File: /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh

Fatal error in Module uvm_pkg at /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh line 27

HDL call sequence:

Stopped at /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh 27 Module uvm_pkg

called from /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh 32 Module uvm_pkg

called from /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/base/uvm_cmdline_processor.svh 245 Function uvm_pkg/uvm_cmdline_processor::new

called from /tools/questa-/2020.3/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src/base/uvm_cmdline_processor.svh 61 Function uvm_pkg/uvm_cmdline_processor::get_inst

6

In reply to vardhana:
thank
now it is runing
why it iss giving one mismatch value

Result misMatchtx.sum=0 & sum=2 tx.a=1 tx.b=1 tx.c=0

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @696

begin_time time 64 10

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

Result matchtx.sum=0 & sum=0 tx.a=0 tx.b=0 tx.c=0

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @700

begin_time time 64 20

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

Result matchtx.sum=0 & sum=0 tx.a=0 tx.b=0 tx.c=0

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @704

begin_time time 64 30

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

Result matchtx.sum=2 & sum=2 tx.a=1 tx.b=1 tx.c=0

UVM_INFO verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @ 40: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase

— UVM Report Summary —

** Report counts by severity

UVM_INFO : 2

UVM_WARNING : 0

UVM_ERROR : 0

UVM_FATAL : 0

** Report counts by id

[RNTST] 1

[TEST_DONE] 1

** Note: $finish : C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)

Time: 40 ns Iteration: 50 Instance: /top

1

7

In reply to taufeeq_khan:

In reply to vardhana:
thank
now it is runing
why it iss giving one mismatch value

Result misMatchtx.sum=0 & sum=2 tx.a=1 tx.b=1 tx.c=0

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @696

begin_time time 64 10

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

Result matchtx.sum=0 & sum=0 tx.a=0 tx.b=0 tx.c=0

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @700

begin_time time 64 20

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

Result matchtx.sum=0 & sum=0 tx.a=0 tx.b=0 tx.c=0

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @704

begin_time time 64 30

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

Result matchtx.sum=2 & sum=2 tx.a=1 tx.b=1 tx.c=0

UVM_INFO verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @ 40: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase

— UVM Report Summary —

** Report counts by severity

UVM_INFO : 2

UVM_WARNING : 0

UVM_ERROR : 0

UVM_FATAL : 0

** Report counts by id

[RNTST] 1

[TEST_DONE] 1

** Note: $finish : C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)

Time: 40 ns Iteration: 50 Instance: /top

1

UVM_INFO @ 0: reporter [RNTST] Running test base_test…
Result matchtx.sum=0 & sum=0

Name Type Size Value

tx seq_item - @3729
begin_time time 64 5
depth int 32 'd2
parent sequence (name) string 3 seq
parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq
sequencer string 28 uvm_test_top.env1.agent1.sqr

Result matchtx.sum=3 & sum=3

Name Type Size Value

tx seq_item - @3777
begin_time time 64 15
depth int 32 'd2
parent sequence (name) string 3 seq
parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq
sequencer string 28 uvm_test_top.env1.agent1.sqr

Result matchtx.sum=4 & sum=4

Name Type Size Value

tx seq_item - @3792
begin_time time 64 25
depth int 32 'd2
parent sequence (name) string 3 seq
parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq
sequencer string 28 uvm_test_top.env1.agent1.sqr

Result matchtx.sum=2 & sum=2

Name Type Size Value

tx seq_item - @3752
begin_time time 64 35
depth int 32 'd2
parent sequence (name) string 3 seq
parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq
sequencer string 28 uvm_test_top.env1.agent1.sqr

Result matchtx.sum=5 & sum=5

Name Type Size Value

tx seq_item - @3702
begin_time time 64 45
depth int 32 'd2
parent sequence (name) string 3 seq
parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq
sequencer string 28 uvm_test_top.env1.agent1.sqr

can you post you dut ?

8

In reply to vardhana:

dut
module adder(intf pif);

always@(posedge pif.clk)
begin

	   pif.sum=pif.a + pif.b + pif.c;

end
endmodule