In reply to taufeeq_khan:
Seems like some simulator related issue?
i have modified your code a bit, this might help you.
tx=seq_item::type_id::create(“tx”,this); → sequence_item takes only name as argument
import uvm_pkg::*;
`include "uvm_macros.svh"
class seq_item extends uvm_sequence_item;
`uvm_object_utils(seq_item)
rand bit [1:0]a;
rand bit [1:0]b;
rand bit c;
bit [2:0]sum;
function new(string name="seq_item");
super.new(name);
endfunction
endclass
class base_seq extends uvm_sequence#(seq_item);
seq_item tx;
`uvm_object_utils(base_seq)
function new(string name="base_seq");
super.new(name);
endfunction
task body();
repeat(2) begin
tx=seq_item::type_id::create("tx");
start_item(tx);
assert(tx.randomize);
tx.print();
finish_item(tx);
end
endtask
endclass
class sequencer extends uvm_sequencer#(seq_item);
`uvm_component_utils(sequencer)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
endclass
class driver extends uvm_driver#(seq_item);
seq_item tx;
virtual intf vif;
`uvm_component_utils(driver)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
void'(uvm_config_db #(virtual intf)::get(this,"","pif",vif));
endfunction
task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk);
seq_item_port.get_next_item(tx);
vif.a=tx.a;
vif.b=tx.b;
vif.c=tx.c;
seq_item_port.item_done();
end
endtask
endclass
class monitor extends uvm_monitor;
virtual intf vif;
seq_item tx;
uvm_analysis_port#(seq_item) port;
`uvm_component_utils(monitor)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
void'(uvm_config_db#(virtual intf)::get(this,"","pif",vif));
port=new("port",this);
tx=seq_item::type_id::create("tx",this);
endfunction
task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk);
tx.a=vif.a;
tx.b=vif.b;
tx.c=vif.c;
tx.sum=vif.sum;
port.write(tx);
end
endtask
endclass
class agent extends uvm_agent;
sequencer sqr;
driver dvr;
monitor mon;
`uvm_component_utils(agent)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
sqr=sequencer::type_id::create("sqr",this);
dvr=driver::type_id::create("dvr",this);
mon=monitor::type_id::create("mon",this);
endfunction
function void connect_phase(uvm_phase phase);
dvr.seq_item_port.connect(sqr.seq_item_export);
endfunction
endclass
class scoreboard extends uvm_scoreboard;
seq_item tx;
uvm_analysis_imp#(seq_item,scoreboard) imp;
bit [4:0]sum;
`uvm_component_utils(scoreboard)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
imp=new("imp",this);
tx=seq_item::type_id::create("tx",this);
endfunction
function void write(seq_item tx1);
this.tx=tx1;
sum=tx.a + tx.b +tx.c;
if(sum == tx.sum)
$display( "Result match","tx.sum=%0d & sum=%0d ",tx.sum,sum);
else
$display( "Result misMatch","tx.sum=%0d & sum=%0d ",tx.sum,sum);
endfunction
endclass
class env extends uvm_env;
agent agent1;
scoreboard sb;
`uvm_component_utils(env)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
agent1=agent::type_id::create("agent1",this);
sb=scoreboard::type_id::create("sb",this);
endfunction
function void connect_phase(uvm_phase phase);
agent1.mon.port.connect(sb.imp);
endfunction
endclass
class base_test extends uvm_test;
env env1;
base_seq seq;
`uvm_component_utils(base_test)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
env1=env::type_id::create("env1",this);
seq=base_seq::type_id::create("seq",this);
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this);
seq.start(env1.agent1.sqr);
phase.drop_objection(this);
endtask
endclass
interface intf(input bit clk);
logic [1:0]a,b;
logic c;
logic [2:0]sum;
endinterface
module adder(intf vif);
//always @(posedge vif.clk)
//begin
assign vif.sum=vif.a+vif.b+vif.c;
//end
endmodule
module top;
bit clk;
intf pif(clk);
adder dut(pif);
initial begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),"*","pif",pif);
run_test("base_test");
end
initial begin
clk=0;
forever #5 clk=~clk;
end
endmodule