Hi,
I need to test one scenario for my design, for that purpose I have to write two registers simultaneously from the testcase.
so, how can i access two registers at a time.
sequence and testcase like below.
//sequence
class wrtask extends ahb_seq;
.
.
.
task body();
`uvm_do_with(req,{req.m_hwrite == 1'b1;req.m_hburst == SINGLE;req.m_haddr == addr;req.m_hwdata == data;})
endtask
endclass
//Testcase
class a_bc extends base_test;
`uvm_component_utils(a_bc)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
task run_phase(uvm_phase phase);
wrtask wrtask_1;
super.run_phase(phase);
wrtask_1 = wrtas :: type_id ::create("wrtask_1");
phase.raise_objection(this);
wrtask_1.addr = 16'h0008
wrtask_1.data = 32'h1234_1234;
wrtask_1.start(env.ahb_env.ahb_agent.m_sqr);
wrtask_1.addr = 16'h0018
wrtask_1.data = 32'h5467_4567;
wrtask_1.start(env.ahb_env.ahb_agent.m_sqr);
phase.drop_objection(this);
endtask
i tried like fork and join .but it’s not worked.
Thanks,