How to write two registers at a time in UVM..?

UVM
,
1

Hi,
I need to test one scenario for my design, for that purpose I have to write two registers simultaneously from the testcase.
so, how can i access two registers at a time.
sequence and testcase like below.

//sequence
class wrtask extends ahb_seq;
.
.
.
task body();
	     `uvm_do_with(req,{req.m_hwrite == 1'b1;req.m_hburst == SINGLE;req.m_haddr == addr;req.m_hwdata == data;})
endtask

endclass
  
//Testcase
class a_bc extends base_test;
	`uvm_component_utils(a_bc)
	
	function new(string name,uvm_component parent);
               super.new(name,parent);
        endfunction
	
        function void build_phase(uvm_phase phase);
		super.build_phase(phase);
	endfunction

        task run_phase(uvm_phase phase);
              wrtask wrtask_1;
             super.run_phase(phase);
             wrtask_1	= wrtas :: type_id ::create("wrtask_1");
             phase.raise_objection(this);
                 wrtask_1.addr = 16'h0008	
                 wrtask_1.data = 32'h1234_1234;	
                 wrtask_1.start(env.ahb_env.ahb_agent.m_sqr);
                 
                 wrtask_1.addr = 16'h0018	
                 wrtask_1.data = 32'h5467_4567;	
                 wrtask_1.start(env.ahb_env.ahb_agent.m_sqr);
	     phase.drop_objection(this);
        endtask

i tried like fork and join .but it’s not worked.

Thanks,

2

In reply to Rao.Bee:

How should this work ?. Dou you have 2 busses to access your register model?

3

In reply to chr_sue:
in my uvm environment don’t have register model.
i have only simple driver ,sequencer, agent blocks.

thanks,

4

In reply to Rao.Bee:

On 1 bus you can access registers in the DUT not in parallel but only serial.

5

In reply to chr_sue:

thanks chr_sue,
but how can i access registers simultaneously.
could you provide any suggestion.?

thanks,

6

In reply to Rao.Bee:

You would need 2 pinlevel interfaces, accessing the registers in the DUT. And the DUT has to support this, like a dual port RAM.