How to write the assertions

SystemVerilog
2

In reply to srbeeram:
Rephrasing the requirements:

[list=1]
Following a new “b” signal “a” is asserted after any number of cycles. This is then followed by the signal “a” being deasserted after any number of cycles.


ap: assert property(
    @(posedge clk) $rose(b) |-> a[->1] ##1 !a[->1]);

Note: b[->1] is equivalent to:
!b[*0:$] ##1 b

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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