How to write Constraints for unpacked array

SystemVerilog
,
1 
typedef struct {  
        randc logic dir     ;                    // IPx.x_DIR
        randc logic phase   ;                    // IPx.x_PHASE
   }t_ipx_drv_r_v ; 
typedef  t_ipx_drv_r_v t_ipx_drv_v[9]  ;
// IPx bit vec(4) array
 typedef struct {  
    randc t_ipx_drv_v drv     ;                    // driver configurations (IPx.x_DIR & IPx.x_PHASE)
  }t_ipx_pwm_v ;

// IPX configuration (all inclusive)
  typedef struct{  
    randc t_ipx_pwm_v  pwm ;                    // all other dedicated configurations
  }t_ipx_cnf_v ;

I have written constraints for the unpacked array

constraint c_dir {
	foreach (i_cnf.pwm.drv[i].dir[i]  {
	     i_cnf.pwm.drv[i].dir[i] == 0;
     }

I am getting Error below
“near “{”: syntax error, unexpected ‘{’, expecting ‘)’.”

2

In reply to darshankumarka_vlsi:

Please use code tags making your code easier to read. I have added them for you.

You also did not show all your variable declarations, just typedefs. I think you want

constraint c_dir {
	foreach (i_cnf.pwm.drv[I])  {
	     i_cnf.pwm.drv[i].dir == 0;
     }