How to write assertion on the scenario, when only 4 bits is set as 1 at a time, the signal will be valid?

SystemVerilog
1

Hi,

I need help to write an assertion for following,
signal_a is a 4 bits register, [3:0] signal_a
when only [3:0]signal_a is 1111 (4 bits is written), the signal_a will be asserted
else if when signal_a is written with any 1 or 2 or 3 bits, the signal_a will be no respond.

2

In reply to Ninana:

Hi @Ninana

Your requirements are not clear. How can signal_a itself get asserted when signal_a itself is a 4-bit register? Please clarify.
It sounds more like you’re trying to generate some signal other than signal_a to know when all 4 bits are high? If so, you can just use the bitwise AND operator: &signal_a.

3

In reply to Soofster:
Changing the requirements to something more clear:


module m;
  bit clk, wr, b;
  bit [3:0] a;
  /* a is a 4 bits register, [3:0] a
    when only [3:0]a is 1111 (4 bits is written), the b will be asserted at the next cycle
    else if   a is written with any 1 or 2 or 3 bits, the b will be no respond.*/

    ap_is_not1111: assert property(@ (posedge clk) wr && a != 4'b1111 |-> ##1 !b  );  
    ap_is_1111: assert property(@ (posedge clk)    wr && a == 4'b1111 |-> ##1  b  );  

endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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