How to write a system verilog assumption with all the bits are 1 but only one bit is 0?

SystemVerilog
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4

In reply to plin317:

In reply to wendy:
If you just like to check only one bit is 0, you could use $countones function, in this case, $countones(bus) == 28.

The following should work.

property bchk0;
logic [28:0] old;
@(posedge clk) disable iff (!rstN)
(1’b1, old = bus) |=>
if (bus == old)
($countones(bus) == 28)
else
(($countones(bus) == 28) && ( bus == {old[27:0], old[28]} ));
endproperty
assert property(bchk0);