How to write a system verilog assumption with all the bits are 1 but only one bit is 0?

SystemVerilog
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1

Hi, I have a register with 29 bits, the default value is all 0.
I would like to write an assumption whereby all bits are 1 except one of the bit is 0.
For example, 29’h3FFF_FFFE
I would like to have the value 0 being cycle through bit 0, bit 1, bit 2…bit 29
Is anyone can help to provide the solution in systemverilog assertion?

2

In reply to wendy:

If you just like to check only one bit is 0, you could use $countones function, in this case, $countones(bus) == 28.

3

In reply to wendy:

property count1(clk1, val1);
    int unsigned prvidx = 0;
    @(posedge clk1)
    ($countones(var1) === ($bits(var1) - 1)) |-> ($clog2((~val1))  === prvidx + 1, prvidx = $clog2((~val1)), $display("val1 = %b prvidx =%d", val1, prvidx));
endproperty : count1

can you try this?

thanks!
Nilesh Patel

4

In reply to plin317:

In reply to wendy:
If you just like to check only one bit is 0, you could use $countones function, in this case, $countones(bus) == 28.

The following should work.

property bchk0;
logic [28:0] old;
@(posedge clk) disable iff (!rstN)
(1’b1, old = bus) |=>
if (bus == old)
($countones(bus) == 28)
else
(($countones(bus) == 28) && ( bus == {old[27:0], old[28]} ));
endproperty
assert property(bchk0);

5

In reply to nhp:

Thanks, it works with $countones

6

In reply to plin317:

I tried with this: $countones(bus) == 28
it is working

7

how to check that on which address, the bit value is 0?

8

Use a for loop.

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