How to write a system verilog assumption with all the bits are 1 but only one bit is 0?

SystemVerilog
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3

In reply to wendy:

property count1(clk1, val1);
    int unsigned prvidx = 0;
    @(posedge clk1)
    ($countones(var1) === ($bits(var1) - 1)) |-> ($clog2((~val1))  === prvidx + 1, prvidx = $clog2((~val1)), $display("val1 = %b prvidx =%d", val1, prvidx));
endproperty : count1

can you try this?

thanks!
Nilesh Patel