In reply to ben@SystemVerilog.us:
Here are the 2 solutions, one woth the task approach and one woith SVA.
This is a complete testbench for the assertions.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b;
event e_pass, e_fail;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
// -Falling of signal 'a' is triggering condition.
// -From the fell of 'a', count no of pos edges of signal 'b' within 120ns.
// 120ns is 6 clk periods
// -if count(no of pos edges of 'b' less than or equal to two
// assertion should fail, else (>2) assertion should pass
function int do_count (int d, bit b);
if($rose(b)) return d+1'b1;
else return d;
endfunction
property p_a2b;
int v_count=0;
$fell(a) |-> ( (1, v_count=do_count(v_count, b))[*1:$] intersect (1[*7]))
##0 v_count > 2;
endproperty
// the (1[*7])) account for the start repeat + 6 more
ap_a2b: assert property(@ (posedge clk) p_a2b );
task automatic t_AB;
automatic bit status=0;
automatic int count=0;
fork
begin : the120ns
#120ns;
end
begin : thecount
forever begin : fr1
// count the b's
@(posedge clk);
if($rose(b)) count=count+1'b1;
if(count>2)status=1;
end : fr1
end
join_any
if(status) -> e_pass;
else -> e_fail;
assert(status);
endtask
always @(posedge clk)
if ($fell(a)) fork t_AB();
join_none
initial begin
bit va, vb;
repeat(300) begin
@(posedge clk);
if (!randomize(va, vb) with
{ va dist {1'b1:=1, 1'b0:=10};
vb dist {1'b1:=1, 1'b0:=1};
}) `uvm_error("MYERR", "This is a randomize error")
a <= va;
b <= vb;
end
$stop;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
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