How to write a assertion to check no of pos edges of a clock within 120ns from trigger condition

SystemVerilog
, ,
4

In reply to ben@SystemVerilog.us:

Be cause you have an analog type of requirement (the 120ns). I would use tasks, as described in my paper,link below.


task automatic t_AB;
bit status;
int count:
if ($fell(a)) 
fork 
begin : the120ns
#120ns
end
begin : thecount
// count the b's
Statis=1: // under count values
end
join_any
assert(status);
endtask 
always @(posedge clk) 
fork t_AB(); 
join_none

Above is a framework for your code, you need to tune it.
See my paper 1) SVA Alternative for Complex Assertions
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Ben Cohen
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  1. Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment

Hi Ben,

In your code I see that on every posedge clk, the task is called under a fork. This will just create multiple threads. Instead of this can’t we just move the alywas @posedge clk internal to the mutiple processes running inside fork .join. something like this:

task automatic t_AB;
bit status;
int count:
bit a_fall;

always@(posedge clock) begin: block_to_disable
if ($fell(a)) begin
a_fall = 1;
disable block_to_disable;
end

fork
begin
begin : the120ns
#120ns: //wait till timeout (excute a delay sequence here that waits till 120ns)
end

begin : thecount
// count the b’s

always@(posegde clk)
$rose(b)|->(count ++);
end
end
end
join_any
assert(count>=2);
endtask

fork t_AB();
join_none