How to write a assertion to check no of pos edges of a clock within 120ns from trigger condition

SystemVerilog
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3

In reply to ben@SystemVerilog.us:
I am new to writing SVA assertions. This might not be 100% correct, I am just thinking this from a logic perspective on how to write it as of now.
task automatic t_AB;
bit status;
int count:
if ($fell(a))
fork
begin : the120ns
//#120ns: //wait till timeout
begin
`uvm_do_with(delay, {delay == 12000;}); //put some delay here equivalent to 120 ns units. can be a delay sequence too like here.
end

 begin : thecount
  // count the b's
   //@(posegde clk) // the process inside fork is already spawned  on a posedge clk.
   $rose(b)|->(count ++);
 end

end
join_any
assert(count>=2);
endtask
always @(posedge clk)
fork t_AB();
join_none