Be cause you have an analog type of requirement (the 120ns). I would use tasks, as described in my paper,link below.
task automatic t_AB;
bit status;
int count:
if ($fell(a))
fork
begin : the120ns
#120ns
end
begin : thecount
// count the b's
Statis=1: // under count values
end
join_any
assert(status);
endtask
always @(posedge clk)
fork t_AB();
join_none
Above is a framework for your code, you need to tune it.
See my paper 1) SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115