How to use the arguments of two different sequences for comparing in a third sequence using Assertions?

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

1.Here my clock itself is scl.So,I cant check the START condition if I use @(posedge scl) as my clocking event.So, I used @(negedge sda).

2.After START was detected,at the next immediate posedge of SCL,checking of cfg.slave_addr_tran ==1’b1 should be done.So, I thought of using a task which will produce delay of one posedge of scl.