In reply to rajan passionate:
Consider using the within sequence operator. The sequence containment within specifies a sequence occurring within another sequence.
Note: (seq1 within seq2) is equivalent to:
((1[*0:] ##1 seq1 ##1 1[*0:]) intersect seq2 )
You also seem to overuse the sequence declaration, and I see no use for your task.
I don’t know if this assertion will work for you, but I suggest something like.
// When SCL is HIGH and before it goes LOW,
// SDA should go LOW.(Here SDA and SCL start from being HIGH initially)
ap_scl: assert property(
@ (posedge some_clock) $rose(scl)|-> !sda[->1] within $fell(scl)[->1]);
// @ (posedge some_clock) $rose(scl)|-> !sda[->1] within ($fell(scl) && sda)[->1]);
// A pootential other option.
// As far as "(1'b1,posedge_delay)|->(slave_addr_tran==1'b1)"
// I have no idea as to what you are talking about.
// If there is a relationship between $fell(sda) and slave_addr_tran,
// write another assertion
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115