How to use the arguments of two different sequences for comparing in a third sequence using Assertions?

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Thanks for the reply Ben.Actually I am trying to write assertions for I2C protocol where I need to check the following scenarios.

1.START condition

When SCL is HIGH and before it goes LOW, SDA should go LOW.(Here SDA and SCL start from being HIGH initially)

2.The START condition is followed by checking of config class variable being 1 at posedge of SCL.

How to generate actual delays instead of Cycle delays?

I wrote a code like this will it work?If not please suggest me a better method sir.



 sequence s1;

	@(negedge I2C_INTERFACE.sda) (I2C_INTERFACE.scl==1);
endsequence

task posedge_delay();

	@(posedge I2C_INTERFACE.scl);

endtask

property p1;

	@(negedge I2C_INTERFACE.sda) s1;

endproperty





property p5;

	@ (posedge I2C_INTERFACE.scl)	s1|->(1'b1,posedge_delay)|->(slave_addr_tran==1'b1);


endproperty