How to use register values of a class inside a module

SystemVerilog
1

Hi,

I am using a module timing check,in that I need the values given in some register.How I can use the value inside my module.

example:
class address_check extends uvm_reg;

max.configure(this, 6, 8, “RO”, 0, `UVM_REG_DATA_WIDTH’h170e>>8, 1, 1, 1);
max = max.value[5:0];

…
endclass

module address();
reg [4:0]adr;
address_check am;
initial begin
adr = am.max.value[4:0];
end
endmodule

if i am using above it is giving error undefined am:

Thanks

2

The problem I see is that the “am” object is not instanced. Yo could either instance it with a new or create, or you can declare in the class a static object. In that case, per 1800’2012 section 8.9, “The static class properties can be used without creating an object of that type.” Below are a couple of changes I made.

class address_check extends uvm_reg;
  max.configure(this, 6, 8, "RO", 0, `UVM_REG_DATA_WIDTH'h170e>>8, 1, 1, 1);
  max = max.value[5:0];
  // Adding this 
  static int max_int=max.value[4:0];
...
endclass

module address();
  reg [4:0]adr;
  address_check am=new(); // added the new 
  initial begin
  	adr=address_check.max_int;  // One option 
    adr = am.max.value[4:0];   // Another option, needed the new()
   end
endmodule

8.9 Static class properties
The previous examples have only declared instance class properties. Each instance of the class (i.e., each object of type Packet) has its own copy of each of its six variables. Sometimes only one version of a variable is required to be shared by all instances. These class properties are created using the keyword static. Thus, for example, in the following case, all instances of a class need access to a common file descriptor:
class Packet ;
static integer fileID = $fopen( “data”, “r” );
Now, fileID shall be created and initialized once. Thereafter, every Packet object can access the file descriptor in the usual way:
Packet p;
c = $fgetc( p.fileID );
*** The static class properties can be used without creating an object of that type.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Hi ben,

Thanks for your reply.
I tried the second option by adding new in the module but compiler is giving error.
I tried to take the instance of the class in another class and then accessing the value. But that also didn’t worked for me.

class address_check extends uvm_reg;
max.configure(this, 6, 8, “RO”, 0, `UVM_REG_DATA_WIDTH’h170e>>8, 1, 1, 1);
max = max.value[5:0];
…
endclass

class check extends uvm_reg;
address_check adr;
end class

module address();
reg [4:0]temp;
check chk = new();----------- in this part compiler giving error of unexpected =, if not doing a new am not able fetch the value.

initial begin
temp = chk.adr.max.value4:0];
end
endmodule

I was taking reference from LRM but in that I didn’t find, use of method new of class instance inside the module.

Thanks

4

In reply to myselfprakhar:

Should have worked. In any case, try putting the new inside the initial statement.
Ben

5

In reply to ben@SystemVerilog.us:

Following code compiled OK

class C;
	function new();
	endfunction
  static int x=10; 
endclass

module m; 
	int y; 
	C c=new(); 
	initial begin 
		y=c.x; 
		c=null; 
		y=c.x;
		c=new(); 
		c.x=8; 
	end 
endmodule

Ben