In reply to ben@SystemVerilog.us:
Hi ben,
Thanks for your reply.
I tried the second option by adding new in the module but compiler is giving error.
I tried to take the instance of the class in another class and then accessing the value. But that also didn’t worked for me.
class address_check extends uvm_reg;
max.configure(this, 6, 8, “RO”, 0, `UVM_REG_DATA_WIDTH’h170e>>8, 1, 1, 1);
max = max.value[5:0];
…
endclass
class check extends uvm_reg;
address_check adr;
end class
module address();
reg [4:0]temp;
check chk = new();----------- in this part compiler giving error of unexpected =, if not doing a new am not able fetch the value.
initial begin
temp = chk.adr.max.value4:0];
end
endmodule
I was taking reference from LRM but in that I didn’t find, use of method new of class instance inside the module.
Thanks