Is there a way to do this in a loop (generate or otherwise)? Especially interesting if the width is a parameter and not a constant.
My attempts have failed as:
I couldn’t modify the wire name identifier at the correct part of the process
I tried using concatenation using macros (``), but macro elaboration is done before the loop unrolling and thus fails.
I don’t believe you can do this directly in Verilog/SV (Unless Dave decides to surprise me and teach me one more today :-)). However, a simple pre-processor can do this:
module m();
wire bus[500:0];
//@ for my $i (0..500) {
assign bus[$i] = my_wire_$i;
//@ }
endmodule : m