How to use a inout port in read and write operation using assign statement

SystemVerilog
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1

hii…
I am trying to read and write operation in a single port.Using a assign statement and high impedence(z) concept.If i am doing write operation the impedence will be the zero. In read operation the impedence will be high.
How to achive?

Thanks in advancce

2

In reply to Rajaraman R:

You have two choices. You can use a read/write control signal. In this case, the port is an output when the control is 1, else it can be used as an input when control is 0.

assign myport = control ? data : 'z;

Or you can procedurally assign a register with data when used as an output, and assign it to 'z when used as an input.

logic myport_reg;

assign myport = myport_reg;

// in procedural code
    myport_reg <= data; // myport becomes an output
    myport_reg <= 'z; // myport becomes an input
3

In reply to dave_59:

In reply to Rajaraman R:
You have two choices. You can use a read/write control signal. In this case, the port is an output when the control is 1, else it can be used as an input when control is 0.

assign myport = control ? data : 'z;

From a style point of view, I like this approach as it clearly demonstrates a tri-state driver.

Or you can procedurally assign a register with data when used as an output, and assign it to 'z when used as an input.

logic myport_reg;
assign myport = myport_reg;] 
// in procedural code
myport_reg <= data; // myport becomes an output
myport_reg <= 'z; // myport becomes an input

This works, but looks awkward since registers do not load Zs.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us