How to use a inout port in read and write operation using assign statement

SystemVerilog
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2

In reply to Rajaraman R:

You have two choices. You can use a read/write control signal. In this case, the port is an output when the control is 1, else it can be used as an input when control is 0.

assign myport = control ? data : 'z;

Or you can procedurally assign a register with data when used as an output, and assign it to 'z when used as an input.

logic myport_reg;

assign myport = myport_reg;

// in procedural code
    myport_reg <= data; // myport becomes an output
    myport_reg <= 'z; // myport becomes an input