Verification Academy
How to switch between RTL and GATE LEVEL paths wihtout updating build block/register model?
UVM
UVM-RAL-systemverilog-ralmodelling
,
UVM
superUVM
June 2, 2021, 5:51pm
3
In reply to
KillSteal
:
yes, that is one way. I was looking for some better way.
show post in topic