IMPORTANT NOTICE:
Please be advised that the Verification Academy Forums will be offline for scheduled maintenance on Sunday, November 9th at 1:00 AM US/Pacific.
Verification Academy
How to switch between RTL and GATE LEVEL paths wihtout updating build block/register model?
UVM
UVM-RAL-systemverilog-ralmodelling
,
UVM
KillSteal
June 2, 2021, 4:23am
2
Wouldn’t tick defines suffice ?
show post in topic