In reply to shparekh:
SystemVerilog has no feature to parameterize the selection of a package to import.
You might consider putting what was inside your packages into a set of interface, then then connecting the desired interface to the port of your module.
If your package was just a set of parameter values, you might consider creating a struct as a parameter and passing different struct values as a parameter override.
If this doesn’t work for you or does not make sense, you’ll need to provide a better picture of what you are trying to accomplish.