How to sample a UVM monitor if clock is not there

UVM
,
1

Hi,

I have a UVM monitor, the input to which 11 parallel data signals are coming. I have 12 bit repair field based on the configuration the data fields are changing. I can’t sample at the clock edge since it will slow down the system. How to sample the data signals and sample the signal where there is a change and it will be a sing bit.That signl I need to sample and send through the analysis port. At what reference point i need to sample.

Thanks
Suvendra

2

In reply to kulua:

I can’t sample at the clock edge since it will slow down the system.

What do you mean by this? I assume that by “system” you mean the simulation. How does sampling at the data rate cause a slowdown? If there is only 1 bit per clock, the sampling code could gather multiple bits into a data word.

3

In reply to kulua:

task run_phase(uvm_phase);
forever begin
@(mon_vif.data[10:0]);
`uvm_info(get_type_name(), $sformatf(“The data is ready to sample”), UVM_MEDIUM)
end
endtask:run_phase

Any of the data bit changes, it will sample.
clk works as well without hitting the simulation performance while sampling in the monitor.

sampling on the clk is nothing but single bit signal and sampling on data will be 11 bits.
hope this helps.
thanks!