How to round real type number?

SystemVerilog
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1

What is the best way to round a real type in systemVerilog according:

Case positive:
if fraction >= 0.5 —> round return the “integer part” + 1 (for example 4.5 —>5)
if fraction < 0.5 —> round return the “integer part” (for example 4.2 —>4)

Case negative:
if fraction >= 0.5 —> round return the “integer part” -1 (for example -4.5 —>-5)
if fraction < 0.5 —> round return the “integer part” (for example -4.2 —> -4)

2

Use an int cast.

module top;
   real A;
   initial begin
      A = 3.4;
      A = int'(A);
      $display(A);
      A = 3.5;
      A = int'(A);
      $display(A);
      A = 3.6;
      A = int'(A);
      $display(A);
   end 
endmodule
3

In reply to dave_59:

Use an int cast.

module top;
real A;
initial begin
A = 3.4;
A = int'(A);
$display(A);
A = 3.5;
A = int'(A);
$display(A);
A = 3.6;
A = int'(A);
$display(A);
end 
endmodule

Hi Dave,

module top;
initial begin
int C;
C = $rtoi(44 *(16/44));
$display("The result = 'd%0d and 'b%0b",C,C);
end
endmodule

In the above example, the output C is zero. How to get non-zero value? Can you please help me out with this regard.

Thank you,

Regards,
Muneeb Ulla Shariff

4

In reply to muneebullashariff:
Because (16/44) gets evaluated using integer arithmetic. In order to get a fractional result, at least one of the operands needs to be real. i.e. (16.0/44)