How to resolve Fatal: (vsim-3695) QuestaSim or Error-[SV-UIP] Unconnected interface port

SystemVerilog
1

How can the following error be resolved?
What are the possible causes?

Error-[SV-UIP] Unconnected interface port on VCS
or
Fatal: (vsim-3695) QuestaSim

is there any compiler directive to ignore the error?

I encountered this error while trying to simulate the following code:
>>> link to eda playground

2

In reply to Zafar:

Several issues/recommendations:

  • You should have only one module/interface per file, with the filename matching the contained module/interface
  • The file testbench.sv has no testbench, only a module and interface. These are interpreted as top-level modules which result in the error you are seeing. You need to create a testbench.
3

In reply to cgales:

  • I do have a testbench too but with the testbench I am getting the same error. So I thought of trying that way, compiling without the testbench. should share with the testbench?

Thank you very much for your recommendations.

4

In reply to Zafar:

You will need to share your entire environment if you want assistance.

5

In reply to cgales:

I was trying to simulate the following axi project:

6

In reply to Zafar:

You want to use the provided scripts to compile and run.

7

In reply to Zafar:

You should check the validity of the error. Do you have a top-level module with an interface port? Do you have an inteface port that you forgot to connect? As the error message says, you are not allow to leave it unconnected.