How to resolve Fatal: (vsim-3695) QuestaSim or Error-[SV-UIP] Unconnected interface port

SystemVerilog
2

In reply to Zafar:

Several issues/recommendations:

  • You should have only one module/interface per file, with the filename matching the contained module/interface
  • The file testbench.sv has no testbench, only a module and interface. These are interpreted as top-level modules which result in the error you are seeing. You need to create a testbench.