How to resolve Fatal: (vsim-3695) QuestaSim or Error-[SV-UIP] Unconnected interface port

SystemVerilog
3

In reply to cgales:

  • I do have a testbench too but with the testbench I am getting the same error. So I thought of trying that way, compiling without the testbench. should share with the testbench?

Thank you very much for your recommendations.