How to prove independency between parameters using formal verification?

SystemVerilog
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1

I am looking for solutions to prove independency between parameters (generics in VHDL or parameter in Verilog/SystemVerilog) using formal verification.

2

In reply to aman.kumar:

What does it mean for two parameters to be independent of one another?

3

In reply to sbellock:

It means that changing value for one parameter does not affects the other parameter. Kind of mutually exclusive. Other way of thinking about this would be one parameter doesn’t falls under the cone of influence of the other parameter.

4

So something like


// A and B are independent.
parameter int A = 8;
parameter int B = 16;



// B depends on A.
parameter int A = 8;
parameter int B = A * 2;

?