I am trying to figure out what is the correct way of achieving the following objective with the use of inheritance.
base_test extends uvm_test
dut1_base_test extends base_test
dut2_base_test extends base_test
my_test extends (sometimes dut1_base_test, sometimes dut2_base_test). ← how do I do this?
dut1_base_test and dut2_base test have all the same tasks and function, but the tasks/function implementation is different. base_test also has all the same tasks and functions with empty implementations.
How do I programmatically tell my_test to extend from base_test1 or base_test2? The test does not need to change, only the underlying implementations of its tasks and functions.
the goal is that sometimes my_test will run against dut1 and sometimes against dut2. Dut1 and Dut2 look the same from the outside (same I/o) and are picked based on a verilog configuration/libmap.
I can’t quite wrap my head around class overriding as we have a chain of inheritance. if my_test extends base_test and then I override base_test to dut1_base_test, then it would seem like dut1_base_test now extends itself, as it’s parent has been overridden.
at this stage everything works if I only change the code from “extends dut1_base_test” to extends “dut2_base_test”. But obviously I do not want to change the code every time I want to do this. is there a way to do this right with factory overrides?
Appreciate any help on how to approach this correctly.