How to pass hierarchical path as string

SystemVerilog
1

Hi, I need to pass the hierarchichal path as a string to the task.

For example,

task loadmem (input_file, "top.top1.mem_array)

<< Load top.top1.mem_array with input_file contents>>

endtask

How do I do this in sv?

2

Can’t be done this way in SystemVerilog. The language has no way to convert strings to hierarchical references; everything must be statically typed in order for the compiler to generate code to execute statements involving expressions. Here are some options:

  1. Usually memories are modeled behaviorally - i.e. not synthesizable. Have it provide a function that you can call to load it given a string filename.
  2. If you know the exact type of the memory, you can pass the memory to the function by a reference argument.
  3. You can use the PLI C interface to access memories directly via a string pathname. The uvm_mem classes have implemented this for you already. Just remember to limit PLI access to just the memories you need because allowing string access to any object in your design via the C interface is a severe performance penalty regardless of whether you access the memory or not.

BTW, you should always use functions instead of tasks for non-time consuming routines. Functions cannot call tasks. (except when forked off)

3

In reply to dave_59:

So there is no way to store hiercachical path in a variable as object or something and possibly pass them to a function / method?

thanks much

4

In reply to stanzani:

You might be able to pass a string to a function and use a tool specific function using that string.

We do this sometimes to bypass loading registers…

example using Modelsim…

$signal_force(“/top/dut/register/mode”, $psprintf(“%b”, 4’h0), 0,3,-1,1);

You can store “/top/dut/register/mode” as a string.

5

In reply to dave_59:
Is there any way to access hierarchy in DPI-C?

6

In reply to lokeshmahor:

7

In reply to dave_59:
Thank you dave

We have implemented it with vpi its working for us.