Can’t be done this way in SystemVerilog. The language has no way to convert strings to hierarchical references; everything must be statically typed in order for the compiler to generate code to execute statements involving expressions. Here are some options:
- Usually memories are modeled behaviorally - i.e. not synthesizable. Have it provide a function that you can call to load it given a string filename.
- If you know the exact type of the memory, you can pass the memory to the function by a reference argument.
- You can use the PLI C interface to access memories directly via a string pathname. The uvm_mem classes have implemented this for you already. Just remember to limit PLI access to just the memories you need because allowing string access to any object in your design via the C interface is a severe performance penalty regardless of whether you access the memory or not.
BTW, you should always use functions instead of tasks for non-time consuming routines. Functions cannot call tasks. (except when forked off)