How to override uvm_top.set_timeout() in the same phase and same test case?

UVM
, ,
1

i have a situation where i need to add extra time with every pass but i observe that the test runs only till 400us. when num_passes is greater than 2, i need more time to run the passes but im getting timeout as it is taking only 400us.
task drive();
uvm_top.set_timeout(400us);
if(num_passes> 2) begin
for (int i = 0; i < num_passes; i++) begin
current_time = $realtime/1us + 1; //Get the current time in microseconds
timeout = current_time*1us + 2000us; //Add 2000 us extra for every pass
uvm_top.set_timeout(timeout);
pass(i);
end
end
endtask

i have seen examples like override the timeout in different phases and in different test cases but not in a scenario like this.
Could someone please help with this?

2

In reply to Liiiiiz:

There are 2 different ways to postpone the end of the simulation.
You can set the timeout. This is to delay the end of the simulation by a certain time.
Or you are overriding the pahse_ready_to_end. This ios a task you can implement and wait for the simulation to process any oustanding operations. The finish is called.

3

In reply to chr_sue:

If you know the number of passes in a component, you could raise an objection in a repeat loop. Then drop an objection at the end of each pass.