How to override uvm_top.set_timeout() in the same phase and same test case?

[chr_sue]

In reply to Liiiiiz:

There are 2 different ways to postpone the end of the simulation.
You can set the timeout. This is to delay the end of the simulation by a certain time.
Or you are overriding the pahse_ready_to_end. This ios a task you can implement and wait for the simulation to process any oustanding operations. The finish is called.