Need an advice… Is there a way in SystemVerilog to over riding existing method? Something like the “is only {” in Specman…
Reason I’m asking becuase here is what I’m trying to do:
I’m trying to add a “direct testing support” to my existing generator module… Means I want to add an “empty” method inside one of my methods in the generator, and from a seperate file (the “direct test”) to actually write the content of that method.
This method will be used to override any randomization that happened in the generator.
So the code should look something like this:
generator.sv:
class C_Generator; // generating sequence of Operations
…
task run;
repeat (num_operations) begin
Operation = new();
void’(Operation.randomize());
override_operation(Operation);<— how to extend this in a seperate file?
Gen2Dr.put(Operation);
end
endtask
In SystemVerilog, you can get the behavior you are looking for by making the task virtual, and extending the class with a method that overrides the override_operation().
class C_generator_ext extends C_generator;
virtual task override_operation;
// any code before
// super.override_operation();
// any code after - is also
endtask
endclass
Whether you call super.override_operation() or not is the difference between is-only or is-also.
The you construct the extended class and place it’s handle in the same class variable that would have held a handle to C_generator.
The UVM provides a standard factory mechanism to do this for you, but if you are not using it, you can read this older article on how to do it.
thanks Dave, but extending the C_generator creates a new class, no?
In that case, I’m not able to override the “super” function, but creating a new function in a new class.
What do you think?
Here you can use the concept of polymorphism , by extending class you can override the function and task of base class if you declare virtual methods in base class these kind of thing generally used for callbacks.