In SystemVerilog, you can get the behavior you are looking for by making the task virtual, and extending the class with a method that overrides the override_operation().
class C_generator_ext extends C_generator;
virtual task override_operation;
// any code before
// super.override_operation();
// any code after - is also
endtask
endclass
Whether you call super.override_operation() or not is the difference between is-only or is-also.
The you construct the extended class and place it’s handle in the same class variable that would have held a handle to C_generator.
The UVM provides a standard factory mechanism to do this for you, but if you are not using it, you can read this older article on how to do it.