In reply to chr_sue:
In reply to UVM_LOVE:
The register model contains the information how the backdoor can access the registers by using add_hdl_path_slice and add_hdl_path.
These 2 configuration methods are specifying the path to the single regs.
In your code example you do not read from the design registers because you did not sett the path correctly.
Ah… It too hard to get a Normal register test tutorial. I got from verification.com.
I think this example is something wrong and too hard to understand accessibility for uvm reg model.
Anyway this example use .write() and .read() methods for example. and eventually these methods are working at the point of result view.
So I add in the middle of test sequence “.update()” or “.mirror()”…
AS your answer, This example onlt for test .write() and .read(). am I understand correctly?
If I don’t use BACKDOOR access, Do I need “add_hdl_path_slice” and “add_hdl_path”?
If yes, I modify my example only FRONTDOOR, U RAL - EDA Playground
But still it has mismatched between mirrored values and dut values after .write()
Could you guide me Sir?