How to handle backdoor paths for a design in VHDL?

UVM
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1

HI,

I am trying out backdoor access to a HDL path in VHDL design and I get fatal error when I am checking correctness of HDL path. To me it seems like DPI function doesn’t support VHDL based paths. What would you suggest to handle such scenario? As I can’t find much in related article.

Best Regards,
Usman

2

In reply to muhammad_usman_tanveer:

I have a UVM Register testbench working with an example VHDL DUT.

The UVM Register block build method uses the add_hdl_path method to define the path as shown below
I had an instance ‘dut’ in my testbench and my registers resides in that level of the hierarchy.

  virtual function void build();

     add_hdl_path("top.dut");

     RegA_h = RegA::type_id::create("RegA_h");
     RegA_h.configure(this, null, "data_RegA_h_local");
     RegA_h.build();

     RegB_h = RegB::type_id::create("RegB_h");
     RegB_h.configure(this, null, "data_RegB_h_local");
     RegB_h.build();

Hope that helps
Graeme

3

In reply to graeme_jessiman:

Hi Graeme,

I had such method call in my uvm_reg_block class. And in my uvm_reg class each field has its own hdl path.

I got dpi call related fatal error message while trying out uvm built-in sequence for checking correctness of HDL paths. This leads me to the observation that dpi calls might not support VHDL related paths.

Best Regards,
Usman