How to handle backdoor paths for a design in VHDL?

UVM
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2

In reply to muhammad_usman_tanveer:

I have a UVM Register testbench working with an example VHDL DUT.

The UVM Register block build method uses the add_hdl_path method to define the path as shown below
I had an instance ‘dut’ in my testbench and my registers resides in that level of the hierarchy.

  virtual function void build();

     add_hdl_path("top.dut");

     RegA_h = RegA::type_id::create("RegA_h");
     RegA_h.configure(this, null, "data_RegA_h_local");
     RegA_h.build();

     RegB_h = RegB::type_id::create("RegB_h");
     RegB_h.configure(this, null, "data_RegB_h_local");
     RegB_h.build();

Hope that helps
Graeme