I’m running into an issue re-using assertions in gate-level sims.
At the top level of our testbench, I have a number of control bits that are used as the disable conditions for our assertions. The problem is that in gate-level sim, all those signals are gone, presumably as they don’t connect to the design.
Right now I’m working around the issue by defining a series of gate-sim specific behavioral tasks that uses $asserton and $assertoff to control assertions, but I have to write one statement for each and every assertion out there and it seems to me that there surely must be a better and cleaner way to do this.
Any recommendations on how one can go about controlling assertion disables that functions smoothly both in regular sim and gate-level sim?
Does it help to use an command line option “+DISABLE_IN_GLS”. When you run simulation with this command line option, the assertion will be disabled.
disable_bit = disable_bit || $test$plusargs(“DISABLE_IN_GLS”);
Well actually, i want to run the assertion in GLS also.
But your idea seems like it could work if i use plusargs to replace the disable bits. Something like