How to handle a struct initialization in systemverilog

SystemVerilog
1

I have the code as below but it failed at compile error.

typedef struct {
    logic [7:0] mem_data[1024];
} mem_blk;

mem_blk m_mem[];
...
...
logic [7:0] data = 'h12;
m_mem[3].mem_data[0] = data;

the error information is :
Error- [SV-RTOOBAW] Reference to out of bound array word

2

In reply to zz8318:

Did you allocate for m_mem dynamic array? What’s the size? Can you post the completed code?

3

In reply to chris_le:

The size is not determined for the verification purpose actually…

and I pasted all related code so may I know how to allocate the dynamic array ?

4

In reply to zz8318:
Dynamic arrays need to be allocated using new, or a copy from an array of the same time. So you need to do

m_mem = new[4];

Before you can reference m_mem[3].

Or maybe you meant to declare an associative array instead of a dynamic array.

mem_blk m_mem[bit [15:0]];

Then a write to m_mem[3] allocates that entry.

5

In reply to chris_le:

typedef struct {
logic [7:0] mem_data[1024];
} mem_blk;

mem_blk m_mem;

logic [31:0] addr = randomize(); // the address is randomized from 0 to 2^32-1
logic [7:0] data = 'h12;
uint32 id = addr / 1024; // uint32 is already typedef in the svh file
m_mem[id].mem_data[0] = data;

6

In reply to zz8318:

Looks like you want an associative array

mem_blk m_mem[uint32];
7

In reply to dave_59:

Thanks a lot