How to handle a struct initialization in systemverilog

SystemVerilog
5

In reply to chris_le:

typedef struct {
logic [7:0] mem_data[1024];
} mem_blk;

mem_blk m_mem;

logic [31:0] addr = randomize(); // the address is randomized from 0 to 2^32-1
logic [7:0] data = 'h12;
uint32 id = addr / 1024; // uint32 is already typedef in the svh file
m_mem[id].mem_data[0] = data;