How to generate unique address from master to multiple slaves

SystemVerilog
5

In reply to Desam:

class a;
 
  parameter N = 10; //no of slaves 
  
  parameter width = 4;
  
  int slaves_width[N];
 
  rand int unsigned add[N],end_[N];
  
 
  constraint unique_add { unique{add};}
  
  constraint size { foreach(end_[i])
    end_[i] == add[i] + this.slaves_width[i]; }
  
  function void pre_randomize( int slaves_width[N] );
                                                   // this is to take width of slaves before 
                                                   //hand
    foreach(slaves_width[i])
      
      this.slaves_width[i] = slaves_width[i];
    
  endfunction
 
  endclass
 
module tb;
 
  a a1;
  int aa[10] = '{10{4}};
  initial
    begin
      a1 = new;
      a1.pre_randomize(aa);
      a1.randomize;
      $display("%p *** %p",a1.add,a1.end_);
      end
endmodule

BUT I am sure there is an other way which i am not aware of. lets wait and see.