How to do a clone of an object?

SystemVerilog
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1

I understand that uvm provides a method for us to do clone and copy. But is there a way to do clone in bare system verilog without methodology?
The idea is to avoid shallow copy and do a deep copy in system verilog.

2

In reply to Sai Raghavendran :

Please see my course SystemVerilog OOP for UVM Verification which covers the concepts of shallow versus deep copy without ever showing any UVM code. Clone is just class construction followed by copy.

3

I have one more question. Say i have a class as below:

class A extends base;
local bit valid;

function new();
 valid = 0;
endfunction

function void copy(base x);
 class abc;
 If ($cast(abc, x)) 
   valid = abc.valid;
endfunction
endclass

the above code is valid, but is it safe to directly access local members of an object?

4

In reply to Sai Raghavendran :

I think you meant to write

function void copy(base x);
 A abc; // abc is a friend to A
 if ($cast(abc, x)) 
   valid = abc.valid;
endfunction

This is safe because you are inside class A referencing a class variable abc whose type is also A. In OOP this is called a friendly access to another to a local or protected members of another class object. Other languages have an explicit keyword friend to allow this kind of access, but in SystemVerilog an object is always a friend to another object of the same class type.