How to disable the assertion from class ? where the assertion is in interface

SystemVerilog
1

Hello,

I have this code. I want to compile this code but it giving me warning.

////////////////////////////////////////////////////////////////////////
//vcs -sverilog +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv parity_error.sv $UVM_HOME/src/dpi/uvm_dpi.cc -CFLAGS -DVCS -timescale=1ns/1ps +acc +vpi -R

import uvm_pkg::*;
`include “uvm.sv”

interface p_l_if(input logic clk, input logic reset, input logic request, input logic grant);

property propseq_prop;
@ (posedge clk)
request ##1 grant;
endproperty

assert_parityerror: assert property (propseq_prop);

endinterface : p_l_if

module dut_link (clk, reset, request, grant);
input clk, reset, request, grant;
endmodule:dut_link

class p_error extends uvm_component;

const local string report_id = “p_error”;

`uvm_component_utils(p_error)

virtual interface p_l_if portlayer_if;

function new (string name, uvm_component parent=null);
super.new(name, parent);
uvm_config_db#(virtual p_l_if)::set(null, “*”,“VIF_portlayer_linklayer”, portlayer_if);
endfunction:new

task my_config();
if(!uvm_config_db#(virtual p_l_if)::get(this, “*”, “VIF_portlayer_linklayer”, portlayer_if))
`uvm_fatal(“No vif”,{"Virtual interface must be set for: ", get_full_name(), “.vif”});
$assertoff(0, portlayer_if.assert_parityerror);
endtask: my_config

endclass:p_error

module testbench();
import uvm_pkg::*;

p_error error_parity;
reg clk, grant, request, reset;
dut_link dut_link( .clk (clk),
.reset (reset),
.request (request),
.grant (grant) );
bind dut_link p_l_if portlayer_if (
.clk (clk),
.reset (reset),
.request (dut_link.request),
.grant (dut_link.grant) );
initial
begin
error_parity = p_error::type_id::create(“error_parity”, null);
uvm_config_db#(virtual p_l_if)::set(null, “*”,“VIF_portlayer_linklayer”,dut_link.portlayer_if);
#1;
$display(“my_config call here”);
error_parity.my_config();
end
always #1 clk = ~clk;
initial
begin
clk=0;
request =0;
grant =0;
#4 request=1;
grant=1;
// $assertoff(1, dut_link.portlayer_if.assert_parityerror);
#4 request=1;
grant=0;

#10;
$finish;
end
endmodule: testbench
///////////////////////////////////////////////////////////////////////////

log file warning.

/////////////////////////////////////////////
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
See 404 for more details.

  (Specify +UVM_NO_RELNOTES to turn off this notice)

my_config call here

Warning-[RA-INVSTR] Not found in design
“$unit .this.portlayer_if.assert_parityerror” not found in design. Ignored
in “$assertoff”.

“parity_error.sv”, 13: testbench.dut_link.portlayer_if.assert_parityerror: started at 1000ps failed at 1000ps
Offending ‘request’
“parity_error.sv”, 13: testbench.dut_link.portlayer_if.assert_parityerror: started at 3000ps failed at 3000ps
Offending ‘request’
“parity_error.sv”, 13: testbench.dut_link.portlayer_if.assert_parityerror: started at 7000ps failed at 9000ps
Offending ‘grant’
“parity_error.sv”, 13: testbench.dut_link.portlayer_if.assert_parityerror: started at 9000ps failed at 11000ps
Offending ‘grant’
“parity_error.sv”, 13: testbench.dut_link.portlayer_if.assert_parityerror: started at 11000ps failed at 13000ps
Offending ‘grant’
“parity_error.sv”, 13: testbench.dut_link.portlayer_if.assert_parityerror: started at 13000ps failed at 15000ps
Offending ‘grant’
“parity_error.sv”, 13: testbench.dut_link.portlayer_if.assert_parityerror: started at 15000ps failed at 17000ps
Offending ‘grant’
$finish called from file “parity_error.sv”, line 90.
$finish at simulation time 18000
///////////////////////////////////////////////////////////

So if I want to remove this warning and disable the assertion from class how i can do that.?

Thank you,
Rakesh

2

Hi Rakesh,

One ways is you can define the below condition in property


disable iff(dis_asrt)

and connect the dis_asrt signal to interface and from sequence you can change the dis_asrt as per requirement.

Thanks,
Vaibhav

3

In reply to Vaibhav Tekale:

Thank you Vaibhav.

Do u have any idea why I am getting a warning.

my_config call here

Warning-[RA-INVSTR] Not found in design
“$unit .this.portlayer_if.assert_parityerror” not found in design. Ignored
in “$assertoff”.

4

I also tried with direct access of object. Still VCS gives same warning.

$assertoff(1, error_parity.portlayer_if.assert_parityerror);

5

In reply to vybhava:

Is there any restriction on Virtual Interface assignment that if we have intereface that bind to any design then it become a static. Now we have same interface as virtual in other class and try to assign a handle to it and access there variable is not possible. ?

6

In reply to rakeshgohil:

I think here there is usage issue or bug in tool. Give me sometime I will get back you on this.

7

In reply to vybhava:

It looks like usage issue. $assertoff should me in same scope as assertion instance. In you code I have moved the $assertoff to interface scope. After moving to interface scope warning message is not coming.

import uvm_pkg::*;
`include “uvm.sv”

interface p_l_if(input logic clk, input logic reset, input logic request, input logic grant);

time t = 1;
typedef enum bit[1:0] {state0 = 2’b01, state1 = 2’b10} Enum0;
property propseq_prop;
@ (posedge clk)
request ##1 grant;
endproperty

assert_parityerror: assert property (propseq_prop);

task my_config();
$assertoff();
endtask: my_config

endinterface : p_l_if

module dut_link (clk, reset, request, grant);
input clk, reset, request, grant;
endmodule:dut_link

class p_error extends uvm_component;

const local string report_id = “p_error”;

`uvm_component_utils(p_error)

virtual interface p_l_if portlayer_if;

function new (string name, uvm_component parent=null);
super.new(name, parent);
uvm_config_db#(virtual p_l_if)::set(null, “*”,“VIF_portlayer_linklayer”, portlayer_if);
endfunction:new

endclass:p_error

module testbench();
import uvm_pkg::*;

p_error error_parity;
reg clk, grant, request, reset;
dut_link dut_link( .clk (clk),
.reset (reset),
.request (request),
.grant (grant) );
bind dut_link p_l_if portlayer_if (
.clk (clk),
.reset (reset),
.request (dut_link.request),
.grant (dut_link.grant) );
initial
begin
error_parity = p_error::type_id::create(“error_parity”, null);
//uvm_config_db#(virtual p_l_if)::set(null, “*”,“VIF_portlayer_linklayer”,dut_link.portlayer_if);
error_parity.portlayer_if = dut_link.portlayer_if;
#1;
$display(“my_config call here”);
//error_parity.portlayer_if.my_config();
end
always #1 clk = ~clk;
initial
begin
clk=0;
request =0;
grant =0;
#4 request=1;
grant=1;
// $assertoff(1, dut_link.portlayer_if.assert_parityerror);
error_parity.portlayer_if.my_config();
#4 request=1;
grant=0;

#10;
$finish;
end
endmodule: testbench