In reply to rkg_:
Simply put the masks to the seq_item and constrain them accordingly.
In reply to chr_sue:
virtual task body();
bit [63:0] rd_data;
bit [63:0] data;
my_seq_item item;
int no_of_regs = 4;
item = my_seq_item::type_id::create("item");
$display ("Calling get all regs ");
get_all_regs(); //to do
// fill the addr_queue;
for (int i = 0; i < no_of_regs; i++)
begin
addr_queue.push_back(32'hf0000000);
addr_queue.push_back(32'hf0000064);
addr_queue.push_back(32'hf0000130);
addr_queue.push_back(32'hf0000134);
addr_queue.push_back(32'hF0000138);
end
$display("addr_queue size = %0d", addr_queue.size);
$display("\taddr_queue = %p",addr_queue);
// addr_queue.shuffle(); // randomize the addresses
// $display("\tshuffle addr_queue = %p",addr_queue);
// Writing all regs
foreach (addr_queue[i]) begin
void'(item.randomize() with {addr == addr_queue[i]; delay == 8; len == 2; opc == 3; tag ==0; mid == 0;prty == 3; });
$display("value of item_addr = %h", item.addr);
svci_master_write(.addr(item.addr), .data(data), .delay(item.delay), .len(item.len), .opc(item.opc),.tag(item.tag),.prty(item.prty), .mid(item.mid));
`uvm_info(get_type_name(), $sformatf("writing req addr = %0h with data = %0h ", item.addr, data), UVM_MEDIUM)
exp_pkt = wr_rd_reg_addr_array_q.pop_front();
expect_mem[addr_queue[i]] = exp_pkt.rdata;
$display("expect_mem[%0h] = %0h",addr_queue[i],expect_mem[addr_queue[i]]);
end
// Reading all regs
foreach (addr_queue[i]) begin
svci_master_read(.addr(addr_queue[i]), .rd_data(rd_data), .delay('h8), .len('h2), .opc('h0), .mid('h0),.tag(0),.prty(3));
if (rd_data == expect_mem[addr_queue[i]])
`uvm_info(get_type_name(), $sformatf("check passed for addr = %0h , rd_data = %h , expected rd_data = %h", addr_queue[i], rd_data,expect_mem[addr_queue[i]]), UVM_MEDIUM)
else
`uvm_error("DATA MISMATCH ERROR", $sformatf("check failed for addr = %0h, actual rd_data = %h , expected rd_data = %h", addr_queue[i],rd_data,expect_mem[addr_queue[i]] ))
end
How to make data for master_write task FFFFF, AAAAA, 55555, 000000 for each set of reg_address.
output should be like
ue size = 20
addr_queue = '{'hf0000000, 'hf0000064, 'hf0000130, 'hf0000134, 'hf0000138, 'hf0000000, 'hf0000064, 'hf0000130, 'hf0000134, 'hf0000138, 'hf0000000, 'hf0000064, 'hf0000130, 'hf0000134, 'hf0000138, 'hf0000000, 'hf0000064, 'hf0000130, 'hf0000134, 'hf0000138}
write_data {ffffffff, fffffff,fffffff,ffffff,fffffff, aaaaaaaa,aaaaaaa,aaaaaaa,aaaaaaa,aaaaaaaa,5555555,55555555…so on} should be on sequence
In reply to rkg_:
As I said, where do you get the wr_msk and the read_mask. If you have them in txt-file you can import them into the testbench in a storage element. Having it a txt-file is not a flexible solution.
In reply to chr_sue:
task body();
bit [31:0] addr[$];
bit [31:0] data[$];
addr = '{32h'f0000000, 32'hf0000064, 32'hf0000130, 32'hf0000134, 32'hf0000138};
data = '{32'hffffffff, 32'haaaaaaaa; 32'h55555555, 32'h00000000};
for (int i = 0; i <= 5; i++)
for (int j = 0; j <= 5; j++)
req.randomize with {addr == addr[j]; data == data [i]};
endtask
In reply to chr_sue:
Hi Chr_sue,
Now same scenario Registers WR/RD i am doing through RAL model. Write Transaction is going well but I am not seeing the read transaction at Interface.
Sequence Code :-
task body;
uvm_status_e status;
uvm_reg_data_t incoming;
bit [31:0] rdata;
if (starting_phase != null)
starting_phase.raise_objection(this);
//Write to the Registers
m_sfr_aon_reg_model.FW_SPARE0.write(status,32'haaaa_5555);
//Read from the registers
m_sfr_aon_reg_model.FW_SPARE0.read(status, rdata);
if (starting_phase != null)
starting_phase.drop_objection(this);
endtask
Adapter Code :
virtual function uvm_sequence_item reg2bus( const ref uvm_reg_bus_op rw );
svci_cmd_trans_pkt cmd_tx = svci_cmd_trans_pkt::type_id::create("cmd_tx");
`uvm_info("REG2BUS",$sformatf("Entered reg2bus at time = %0t",$time),UVM_LOW)
cmd_tx.cmd_addr = rw.addr;
if ( rw.kind == UVM_READ ) begin
$display ("adapter read");
cmd_tx.cmd_opc = 'h0;
//cmd_tx.cmd_len = rd_cmd_len;
cmd_tx.cmd_len = 'h2;
`uvm_info("REG2BUS", $sformatf(" read access = %s", cmd_tx.cmd_opc.name), UVM_LOW)
end
else if ( rw.kind == UVM_WRITE ) begin
$display ("adapter write");
//cmd_tx.cmd_opc = wr_type ? NON_POSTED_WRITE : POSTED_WRITE ;
cmd_tx.cmd_opc = NON_POSTED_WRITE ;
//cmd_tx.cmd_len = wr_cmd_len;
cmd_tx.cmd_len = 'h2;
cmd_tx.cmd_mid = 'h0;
//cmd_tx.cmd_tag = rand_val_tag;
cmd_tx.cmd_tag = 'h0;
cmd_tx.cmd_wdata = rw.addr[2]? {rw.data[31:0],32'h0} : {32'h0,rw.data[31:0]};
//`uvm_info("REG2BUS", $sformatf(" Address = %h, Data = %h, access = %s", cmd_tx.cmd_addr, cmd_tx.cmd_wdata, cmd_tx.cmd_opc.name), UVM_MEDIUM)
`uvm_info("REG2BUS", $sformatf(" Address = %h, Data = %h, access = %s", cmd_tx.cmd_addr, cmd_tx.cmd_wdata, cmd_tx.cmd_opc.name), UVM_LOW)
end
return cmd_tx;
endfunction: reg2bus
virtual function void bus2reg( uvm_sequence_item bus_item, ref uvm_reg_bus_op rw );
svci_cmd_trans_pkt cmd_tx = svci_cmd_trans_pkt::type_id::create("cmd_tx");
svci_rsp_reg_pkt rsp_tx = svci_rsp_reg_pkt ::type_id::create("rsp_tx");
if($cast( rsp_tx, bus_item))begin
rw.kind = ( rsp_tx.rsp_type ==READ ) ? UVM_READ : UVM_WRITE;
rw.addr = rsp_tx.rsp_addr;
rw.data = rsp_tx.rsp_rdata;
rw.status = UVM_IS_OK;
`uvm_info("BUS2REG", $sformatf(" :: 2 :: Address = %h, Data = %h, access = %s", rsp_tx.rsp_addr,rsp_tx.rsp_rdata, rsp_tx.rsp_opc.name), UVM_LOW)
end
endfunction: bus2reg
Could you give me any hint how to debug this scenario ?
when i do not use RAL model it work very well (which has been explained in earlier post).
In reply to rkg_:
The first thing any data (read or write data) used together with the RAL has to be of type
uvm_reg_data_t
Dou you see the write data are arriving in the DUT?
I cannot give you a good advice bedause I do not know which access type the corresponding register has. And your protocol implementation to assign the read data from the data bus might be incorrect.
What is your error message? Which kind of data do you see when reading?
In reply to chr_sue:
Yes, I can see the Write data are arriving in the DUT.
How to make sure " m_sfr_aon_reg_model.FW_SPARE0.read(status, rdata);" this issued the read transaction correctly.
I am getting this msg “$display (“adapter read”);” in my log. does it mean read transaction issued correctly ?
Mentioned registers has RW access and my cmd.opc = 0 for read.
I am not getting any error and getting RDATA 0 since i dont see any read request getting generated.
In reply to rkg_:
Now i can see RDATA is coming .
But seeing the below issue.
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /pga/cadence/xcelium/19.09.003/tools/methodology/UVM/CDNS-1.1d/sv/src/reg/uvm_reg_predictor.svh, line = 151, pos = 12
Scope: worklib.uvm_pkg::uvm_reg_predictor#(svci_pkg::svci_rsp_trans_pkt)@10625_2.write
Time: 1035946034 PS + 61
In reply to rkg_:
Now i can see RDATA is coming .
But seeing the below issue.
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /pga/cadence/xcelium/19.09.003/tools/methodology/UVM/CDNS-1.1d/sv/src/reg/uvm_reg_predictor.svh, line = 151, pos = 12
Scope: worklib.uvm_pkg::uvm_reg_predictor#(svci_pkg::svci_rsp_trans_pkt)@10625_2.write
Time: 1035946034 PS + 61
In reply to rkg_:
The adapter is an individual implementation. If it’s wrong it will indicate all things are fine. But you do not see the expected result.
BTW NEVER use a $display in a UVM testbench. Use instead the `uvm_info.
The NULL pointer dereference is an indication an object does not exist. Look if the transaction svci_rsp_trans_pkt has been constructed.
In reply to chr_sue:
Thanks Chr_sue.
I don’t use $display in my actual code. I have just used for quick debug purpose .
In Waveform, I can see the write transaction and read transaction happing but i see the below msg and Test is getting Passed ?
UVM_INFO @ 1035850ns: reporter [RegModel] Wrote register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE0=0xaaaa5555
UVM_INFO @ 1035882ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE0=0
Where FW_SPARE0 is R/W register. and i expect read value should also same as write value
Here is my question:-
-
Do i need to write the additional checker to compare the write data and read data ? if yes then RAL model is just use for writing the and reading the Registers ?
-
How to take care the masking of registers field during write data and read data compare ?
eg.:- lets say , I have R1 register and i write data is 0xFFFFFFFF and Wr_mask value = 0x00001FF then expected Read data will be 000001FF. I n these scenario where to take care the Wr_mask ? if i will not take care WR data and Read data will not match
In reply to rkg_:
My answers:
(1) You have to implement your own checker. The status is only an indicator for the read/write process to be be OK. You could use in a sequence an associative array where you are storing the WR values. Whne reading you can compare the RD value with the value from the associative array.
(2) You are generating any WR value and masking this value with the WR mask. You are reading the RD value and mask it with the RD mask.